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Re: PIC18F4550 - oscillator settings - FlowCode (pcbbc)

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viki2000
Thank you very much for all your effort and the rates.Indeed was a mistake above, because I was in hurry to shut off the PC before my bus was coming. Was more due to the rush and not paying attention during picture editing and people saying bye around.I will check on Friday your latest recommendations and some I will have some end words. Now I have to prepare myself for a trip.
NP.


I've just searched the datasheet, and found this:
The FSEN bit (UCFG<2>) controls the transceiver speed; setting the bit enables full-speed operation.


So as it seems you need a 48MHz clock for full speed USB with FSEN=1, and as full speed USB is quoted at 12Mbs that means supplied USB clock must be 4 x actual USB data rate?

Then, as low speed USB is 1.5Mbs, we would need a 6MHz clock for that (4 x 1.5 = 6).
So therefore it seems you should select 24MHz as the CPU system clock if you want to support both low and full speed USB 2?

Full speed is provided directly from the PLL output divided by 2 when FSEN=1
Low speed is provided from the primary system clock of 24MHz divided by 4 when FSEN=0

Therefore you should select HS+PLL mode for the system clock and 01 for CPUDIV bits to get a divide by 3 of the 96MHz PLL down to 24MHz for primary CPU clock, and then a further divide of that by 4 to 6MHz and the low speed USB peripheral clock.

Of course all this depends very much on what USB modes you want to support.

Edit: I see it even tells you all the above in note at the bottom of table 2-3, doh!
Legend: All clock frequencies, except 24 MHz, are exclusively associated with full-speed USB operation (USB clock of 48 MHz). Bold is used to highlight clock selections that are compatible with low-speed USB operation (system clock of 24 MHz, USB clock of 6 MHz).

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